Microcomputers have been increasingly used in recent years for the variable speed control of electric motors. However, when individual control circuits constructed for independently controlling respective control objects of an electric motor are controlled together by a microcomputer, the individual control circuits have almost no organic linkage therebetween. As a known example dealing with such a drawback, there is Japanese patent application No. 39254/79.
That is, in this known example, input information indicative of an operating state of an electric motor is digitally, arithmetically and logically processed, and a plurality of reference register groups are provided so that they can individually hold the processed data classified depending on the respective contents of processing. The data held in the reference register groups provide the reference values used in a comparing operation.
There are further provided a plurality of instantaneous register groups holding data indicative of instantaneous states of the motor and others.
And, the reference register groups, the instantaneous register groups, an incrementer/decrementer for incrementing or decrementing the data by unity (1) or decrementing the data to zero, and a comparison circuit, are controlled in a time division mode for the control of the motor.
The stage processing for the control in the time division mode is allotted by outputs C.sub.0 to C.sub.4 a counter called a stage counter, as shown in Table 1. The allotted stage signals are as follows:
(1) PWM-P is used for processing for generating a carrier. PA0 (2) PN-P is used for processing for counting the number of pulses subjected to pulse width modulation. PA0 (3) UTM-P, VTM-P and WTM-P are used for processing for generating pulse width modulation signals of U-phase, V-phase and W-phase respectively. PA0 (4) PULS-P is used for processing for counting external pulses. PA0 (5) PULSW-P is used for processing for generating a constant period of time during which the external pulses are counted.
TABLE 1 ______________________________________ Stage Stage counter signal C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0 ______________________________________ PWM-P x x 0 0 0 PN-P x x 0 0 1 UTM-P x x 0 1 1 VTM-P x x 1 0 0 WTM-P x x 1 0 1 PULS-P x x 1 1 0 PULSW-P 0 0 0 1 0 ______________________________________
The symbol x in Table 1 maybe a "0" or a "1".
However, many processing as shown in Table 1 results in a reduced frequency of processing for each individual control.
The prior art method of generating the period of time T of the carrier providing the fundamental frequency of pulse width modulation is as shown in (a) of FIG. 1.
That is, the data held in the carrier timer included in the instantaneous register groups and the data held in the P1 REG included in the reference register groups and holding data corresponding to the period of time T are compared to generate the period of time T. When the carrier timer is processed according to Table 1, the frequency is controlled in each of the 8 processing stages (the processing frequency) and determined. The frequency f.sub.0 of the fundamental wave of pulse width modulation is expressed by the following equation: EQU f.sub.0 = [ 4 .times. (number of pulses in half cycle) .times. (data of P1 REG) .times. (processing frequency) .times. (processing stage duration) ].sup.-1
Suppose, for example, that the processing frequency is 8 processing stages as shown in Table 1, the processing stage duration is 1 .mu.s, and the number of pulses is 3. Then, when the data of the P1 REG is changed from "87" to "86", the frequency of the fundamental wave changes from 119.73 Hz to 121.12 Hz, and the prior art example is defective in that the resolution in that case is 1.2 % or becomes poorer.